Mask ROM is generally made from a number of cell transistors, each serving as a memory unit. When programming is required, ions are implanted into the channel region of selected memory cells so that threshold voltage of these cells is modified. The `on` or `off` state of each memory cell is thus set. In general, a memory cell is created whenever a word line (WL) crosses over a bit line (BL). The memory cell is formed in the word line covered area between two neighboring bit lines. Each memory cell is capable of storing a binary bit of data, either in a logic state of `0` or `1` depending on whether the channel region of the memory cell is implanted or not.
However, when the generation of the mask ROM fabrication is migrated into deep-sub-micro semiconductor process, the higher integration of the integrated circuit, the smaller size of the semiconductor device. While ions implanted into the channel region of selected memory cells, location of the implanting region may have misalignment, so that shifts the threshold voltage of transistors. If location of the implanting region is misaligned, may be shifted to the direction of word line or bit line, this will directly cause data storage error of the ROM cell and disturb the neighboring implanting regions to affect operation property of the memory cell, especially in the shift of word line direction. A conventional way to resolve the problem is using a phase-shift mask (PSM) to program the ROM code. However, this will greatly increase manufacture cost and time so that PSM is not economic.
In addition, ions are implanted just only one time in programming two-level mask ROM so that the cell transistor only has two cases, ion implanted or not. This results each cell transistor of the two-level mask ROM is indicated to have binary signal of "1" or "0". When memory capacity of two-level mask ROM is required larger, a mount of cell transistors in the two-level mask ROM is increased, so that reducing the integration of the two-level mask ROM, and further reducing yield of the cell transistors.